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data sheet 29319.37i 3959 dmos full-bridge pwm motor driver designed for pulse-width modulated (pwm) current control of dc motors, the a3959sb, a3959slb, and A3959SLP are capable of output currents to 3 a and operating voltages to 50 v. internal fixed off-time pwm current-control timing circuitry can be adjusted via control inputs to operate in slow, fast, and mixed current-decay modes. phase and enable input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm-control signals. internal synchronous rectification control circuitry is provided to reduce power dissipation during pwm operation. internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of supply and charge pump, and crossover-current protection. special power-up sequencing is not required. the a3959sb/slb/slp is a choice of three power packages, a 24-pin plastic dip with a copper batwing tab (package suffix ?b?), a 24-lead plastic soic with a copper batwing tab (package suffix ?lb?), and a thin (<1.2 mm) 28-lead plastic tssop with an exposed thermal pad (suffix ?lp?). in all cases, the power tab is at ground potential and needs no electrical isolation. each package is available in a lead- free version (100% matte tin leadframe). features 3 a, 50 v output rating low r ds(on) outputs (270 m , typical) mixed, fast, and slow current-decay modes synchronous rectification for low power dissipation internal uvlo and thermal-shutdown circuitry crossover-current protection internal oscillator for digital pwm timing a3959slb (soic) absolute maximum ratings load supply voltage, v bb ......................... 50 v output current, i out (repetitive) ........... 3.0 a (peak, <3 s) ................................... 6.0 a logic supply voltage, v dd ....................... 7.0 v logic input voltage range, v in (continuous) ............ -0.3 v to v dd + 0.3 v (t w <30 ns) ............... -1.0 v to v dd + 1.0 v sense voltage, v s (continuo us) .............. 0.5 v (t w <3 s) ........................................... 2.5 v reference voltage, v ref ............................ v dd package power dissipation (t a = 25c), p d a3959sb ........................................ 3.3 w* a3959slb ...................................... 2.5 w* A3959SLP ...................................... 3.1 w* operating temp. range, t a .... -20c to +85c junction temperature, t j ..................... +150c storage temp. range, t s ..... -55c to +150c output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. note that the a3959slb(soic), a3959sb (dip), and A3959SLP (tssop) do not share a common terminal assignment. * double-sided board, one square inch copper each side. see also, layout, page 7. pwm timer v bb 24 23 22 21 20 19 18 17 16 15 14 13 ground ground sleep no connection out b load supply sense out a no connection ext mode ref v reg dwg. pp-069-4 1 2 3 4 5 6 7 8 9 12 11 10 9 ground ground cp cp 2 cp 1 phase v dd enable pfd 2 blank pfd 1 logic supply rosc logic nc nc charge pump 10 part number pb-free* r ja (c/w) r jt (c/w) package packing a3959sb-t yes 38 6 24-pin dip 25 per tube a3959slb-t yes 50 6 24-lead soic 47 per tube a3959slbtr-t yes 50 6 24-lead soic 1000 per ree l A3959SLP-t yes 40 ? 28-pin tssop 50 per tube A3959SLPtr-t yes 40 ? 28-pin tssop 4000 per ree l * pb-based variants are being phased out of the product line. the variants cited in this footnote are in production but have been determined to be last time buy. this classification indicates that sale of this device is currently restricted to existing customer applications. the variants should not be purchased for new design applications because obsolescence in the near future is probable. samples are no longer available. status change: october 31, 2006. deadline for receipt fo last time buy orders: april 27, 2007. these variants include: a3959sb, a3959slb, a3959slbtr, A3959SLP, and A3959SLPtr.
3959 dmos full-bridge pwm mot or driver 2 functional block diagram a3959sb (dip) note that the a3959slb (soic), a3959sb (dip), and A3959SLP (tssop) do not share a common terminal assignment. charge pump bandgap v dd c reg tsd under- voltage & fault detect charge pump bandgap regulator v dd v bb + logic supply v reg cp1 cp cp2 load supply gate drive dwg. fp-048-2a control logic sense r s sleep ext mode phase enable blank pfd1 pfd2 reference buffer & ?10 current sense zero current detect out a out b ref pwm timer v ref c s osc rosc to v dd to v dd pwm timer ?10 v bb 24 23 22 21 20 19 18 17 16 15 14 13 ground ground sleep v reg out b load supply sense out a ext mode ref dwg. pp-069-5a 1 2 3 4 5 6 7 8 9 12 11 10 9 ground ground cp cp 2 cp 1 phase v dd logic supply enable pfd 2 blank pfd 1 q rosc logic charge pump ground ground
3959 dmos full-bridge pwm motor driver www.allegromicro.com 3 electrical characteristics at t a = +25 c, v bb = 50 v, v dd = 5.0 v, v sense = 0.5 v, f pwm < 50 khz (unless noted otherwise) limits characteristics symbol test conditions min. typ. max. units output drivers load supply voltage range v bb operating 9.5 C 50 v during sleep mode 0 C 50 v output leakage current i dss v out = v bb C <1.0 20 a v out = 0 v C <-1.0 -20 a output on resistance r ds(on) source driver, i out = -3 a C 270 300 m ? sink driver, i out = 3 a C 270 300 m ? crossover delay 300 600 1000 ns body diode forward voltage v f source diode, i f = -3 a C C 1.6 v sink diode, i f = 3 a C C 1.6 v load supply current i bb f pwm < 50 khz C 4.0 7.0 ma charge pump on, outputs disabled C 2.0 5.0 ma sleep mode C C 20 a control logic logic supply voltage range v dd operating 4.5 5.0 5.5 v logic input voltage v in(1) 2.0 C C v v in(0) C C 0.8 v logic input current i in(1) v in = 2.0 v C <1.0 20 a (all inputs except enable) i in(0) v in = 0.8 v C <-2.0 -20 a enable input current i in(1) v in = 2.0 v C 40 100 a i in(0) v in = 0.8 v C 16 40 a internal osc frequency f osc r osc shorted to ground 3.25 4.25 5.25 mhz r osc = 51 k ? 3.65 4.25 4.85 mhz reference input volt. range v ref operating 0.0 C v dd v reference input current i ref v ref = v dd CC 1.0 a comparator input offset volt. v io v ref = 0 v C 5.0 C mv continued next page
3959 dmos full-bridge pwm motor driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 4 electrical characteristics at t a = +25 c, v bb = 50 v, v dd = 5.0 v, v sense = 0.5 v, f pwm < 50 khz (unless noted otherwise), continued. limits characteristics symbol test conditions min. typ. max. units control logic reference divider ratio C C 10 C C g m error e gm v ref = v dd CC 4.0 % (note 3) v ref = 0.5 v C C 14 % propagation delay times t pd 0.5 e in to 0.9 e out : pwm change to source on 600 750 1200 ns pwm change to source off 50 150 350 ns pwm change to sink on 600 750 1200 ns pwm change to sink off 50 100 150 ns thermal shutdown temp. t j C 165 C c thermal shutdown hysteresis ? t j C15C c uvlo enable thresholduvlo increasing v dd 3.90 4.2 4.45 v uvlo hysteresis ? uvlo 0.05 0.10 C v logic supply current i dd f pwm < 50 khz C 6.0 10 ma sleep mode C C 2.0 ma notes: 1. typical data is for design information only. 2. negative current is defined as coming out of (sourcing) the specified device terminal. 3. g m error = ([v ref /10] ?v sense )/(v ref /10) where v sense = i trip ? s .
3959 dmos full-bridge pwm motor driver www.allegromicro.com 5 functional description v reg . this internally generated voltage is used to operate the sink-side dmos outputs. the v reg terminal should be decoupled with a 0.22 f capacitor to ground. v reg is internally monitored and in the case of a fault condition, the outputs of the device are disabled. charge pump. the charge pump is used to generate a gate-supply voltage greater than v bb to drive the source- side dmos gates. a 0.22 f ceramic capacitor should be connected between cp1 and cp2 for pumping purposes. a 0.22 f ceramic capacitor should be connected between cp and v bb to act as a reservoir to operate the high-side dmos devices. the cp voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. phase logic. the phase input terminal determines if the device is operating in the ?orward?or ?everse?state. phase out a out b 0 low high 1 high low enable logic. the enable input terminal allows external pwm. enable high turns on the selected sink- source pair. enable low switches off the source driver or the source and sink driver, depending on ext mode, and the load current decays. if enable is kept high, the current will rise until it reaches the level set by the internal current-control circuit. enable outputs 0 chopped 1on ext mode logic. when using external pwm current control, the ext mode input determines the current path during the chopped cycle. with ext mode low, fast decay mode, the opposite pair of selected outputs will be enabled during the off cycle. with ext mode high, slow decay mode, both sink drivers are on with enable low. ext mode decay 0 fast 1 slow current regulation. load current is regulated by an internal fixed off-time pwm control circuit. when the outputs of the dmos h bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (r s ) and the applied analog reference voltage (v ref ): i trip = v ref /10r s at the trip point, the sense comparator resets the source- enable latch, turning off the source driver. the load inductance then causes the current to recirculate for the fixed off-time period. the current path during recirculation is determined by the configuration of slow/ mixed/fast current-decay mode via pfd1 and pfd2. oscillator. the pwm timer is based on an internal oscillator set by a resistor connected from the r osc terminal to v dd . typical value of 4 mhz is set with a 51 k ? resistor. the allowable range of the resistor is from 20 k ? to 100 k ? . f osc = 204 x 10 9 /r osc . if r osc is not pulled up to v dd , it must be shorted to ground. fixed off time. the a3959 is set for a fixed off time of 96 cycles of the internal oscillator, typically 24 s with a 4 mhz oscillator.
3959 dmos full-bridge pwm motor driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6 functional description (continued) internal current-control mode. inputs pfd1 and pfd2 determine the current-decay method after an overcurrent event is detected at the sense input. in slow-decay mode, both sink drivers are turned on for the fixed off-time period. mixed-decay mode starts out in fast-decay mode for a portion (15% or 48%) of the fixed off time, and then is followed by slow decay for the remainder of the period. pfd2 pfd1 % t off decay 0 0 0 slow 0 1 15 mixed 1 0 48 mixed 1 1 100 fast pwm blank timer. when a source driver turns on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. to prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. the blank timer runs after the off-time counter to provide the blanking function. the blank timer is reset when enable is chopped or phase is changed. for external pwm control, a phase change or enable on will trigger the blanking function. the duration is determined by the blank input and the oscilator. blank t blank 0 6/f osc 1 12/f osc synchronous rectification. when a pwm off cycle is triggered, either by an enable chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. the a3959 synchronous rectification feature will turn on the appropriate pair of dmos outputs during the current decay and effectively short out the body diodes with the low r ds(on) driver. this will reduce power dissipation significantly and can eliminate the need for external schottky diodes. synchronous rectification will prevent reversal of load current by turning off all outputs when a zero-current level is detected. shutdown. in the event of a fault (excessive junction temperature, or low voltage on cp or v reg ) the outputs of the device are disabled until the fault condition is removed. at power up, and in the event of low v dd , the uvlo circuit disables the drivers. braking. the braking function is implemented by driving the device in slow-decay mode via extmode and applying an enable chop command. because it is possible to drive current in either direction through the dmos drivers, this configuration effectively shorts out the motor-generated bemf as long as the enable chop mode is asserted. it is important to note that the internal pwm current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. the maximum brake current can be approximated by v bemf /r l . care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. sleep logic. the sleep input terminal is used to minimize power consumption when when not in use. this disables much of the internal circuitry including the regulator and charge pump. logic low will put the device into sleep mode, logic high will allow normal operation. note: if the sleep mode is not used, a 1 k? or 2 k? pull- up resistor is required on the sleep input terminal.
3959 dmos full-bridge pwm motor driver www.allegromicro.com 7 functional description (continued) current sensing. to minimize inaccuracies in sensing the i trip current level, which may be caused by ground trace ir drops, the sense resistor should have an independent ground return to the ground terminal of the device. for low-value sense resistors the ir drops in the pcb sense resistor? traces can be significant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s due to their contact resistance. the maximum value of r s is given as r s 0.5/ i trip where i trip 3.0 a. thermal protection. circuitry turns off all drivers when the junction temperature reaches 165 c typically. it is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. thermal shutdown has a hysteresis of approximately 15 c. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. layout. a star ground system located close to the driver is recommended. the printed wiring board should use a heavy ground plane. for optimum electrical and thermal performance*, the driver should be soldered directly onto the board. the ground side of r s should have an indi- vidual path to the ground terminals of the device. this path should be as short as is possible physically and should not have any other components connected to it. it is recommended that a 0.1 f capacitor be placed between sense and ground as close to the device as possible; the load supply terminal, v bb , should be decoupled with an electrolytic capacitor (> 47 f is recommended) placed as close to the device as is possible. on the 28-lead tssop package, the copper ground plane located under the exposed thermal pad is typically used as a star ground. * the thermal resistance, r ja , and absolute maximum allowable package power dissipation specified on page 1 is measured on a typical two-sided pcb with one square inch copper ground area on each side. with minimal copper on a single-sided pcb (worst-case), the ? package r ja is 40 c/w, ?b?is 77 c/w, and ?p?is 80 c/w. see also, application note 29501.5, improving batwing power dissipation . for specification purposes, the multi-layer high-k board performance graphed here is per jedec standard jesd51. 50 75 100 125 150 5 1 0 allowable package power dissipation in watts temperature in c 4 3 2 25 dwg. gp-049-6 suffix 'b', r ja = 38 c/w suffix 'lp', r ja = 40 c/w suffix 'lb', r ja = 50 c/w double-sided board, 1 sq. in. copper ea. side suffix 'b', r ja = 26 c/w suffix 'lp', r ja = 28 c/w suffix 'lb', r ja = 35 c/w multi-layer high-k board
3959 dmos full-bridge pwm motor driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 8 lbb lp terminal name terminal description (soic) (dip) (tssop) cp reservoir capacitor (typically 0.22 f) 1 24 1 cp 1 & cp 2 the charge pump capacitor (typically 0.22 f) 2 & 3 1 & 2 2 & 3 nc no (internal) connection 4 phase logic input for direction control 4 3 5 rosc oscillator resistor 5 4 6 ground grounds 6, 7 5, 6, 7, 8* 7, 8* logic supply v dd , the low voltage (typically 5 v) supply 8 9 9 enable logic input for enable control 9 10 10 nc no (internal) connection C C 11 pfd 2 logic-level input for fast decay 10 11 12 blank logic-level input for blanking control 11 12 13 pfd 1 logic-level input for fast decay 12 13 14 ref v ref , the load current reference input voltage 13 14 15 ext mode logic input for pwm mode control 14 15 16 no connect no (internal) connection 15 17 out a one of two dmos bridge outputs to the motor 16 16 18 nc no (internal) connection C C 19, 20 sense sense resistor 17 17 21 nc no (internal) connection C C 22 ground grounds 18, 19 18, 19* load supply v bb , the high-current, 9.5 v to 50 v, motor supply 20 20 23 out b one of two dmos bridge outputs to the motor 21 21 24 no connect no (internal) connection 22 25 sleep logic-level input for sleep operation 23 22 26 v reg regulator decoupling capacitor (typically 0.22 f) 24 23 27 ground ground 28* * for the a3959sb (dip) only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. for the A3959SLP (tssop) the grounds at terminals 7, 8, and 28 should be connected together at the exposed pad beneath the device. terminal list
3959 dmos full-bridge pwm motor driver www.allegromicro.com 9 a3959sb dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes: 1. webbed lead frame. leads 6, 7, 18, and 19 are internally one piece. 2. exact body and lead configuration at vendor s option within limits shown. 3. lead spacing tolerance is non-cumulative. 4. lead thickness is measured at seating plane or below. 5. supplied in standard sticks/tubes of 15 devices. 0.014 0.008 0.300 bsc dwg. ma-001-25a in 0.430 max 24 16 12 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 13 1.280 1.230 note 1 7 0.355 0.204 7.62 bsc dwg. ma-001-25a mm 10.92 max 24 1 12 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 13 32.51 31.24 note 1 67
3959 dmos full-bridge pwm motor driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 10 a3959slb notes: 1. exact body and lead configuration at vendor s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. webbed lead frame. leads 6, 7, 18, and 19 are internally one piece. 4. supplied in standard sticks/tubes of 31 devices or add tr to part number for tape and reel. 0 to 8 1 24 13 2 3 0.2992 0.2914 0.6141 0.5985 0.419 0.394 0.020 0.013 0.0926 0.1043 0.0040 min. 0.0125 0.0091 dwg. ma-008-25a in 0.050 bsc note 1 note 3 0.050 0.016 0 to 8 1 24 2 3 7.60 7.40 15.60 15.20 10.65 10.00 0.51 0.33 2.65 2.35 0.10 min. 0.32 0.23 1.27 bsc note 1 note 3 1.27 0.40 dwg. ma-008-25a mm dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions)
3959 dmos full-bridge pwm motor driver www.allegromicro.com 11 A3959SLP 28-pin tssop 0.20 0.09 .008 .004 8o 0o 0.75 0.45 .030 .018 1.20 max .047 0.15 0.00 .006 .000 0.30 0.19 .012 .007 4.5 4.3 .177 .169 6.6 6.2 .260 .244 1 ref .039 5 bsc .200 0.65 bsc .026 3 bsc .118 0.25 bsc .010 9.8 9.6 .386 .378 2 1 28 dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only a exposed thermal pad (bottom surface) gauge plane seating plane a 0.30 bsc .012 6.6 bsc .260 0.75 bsc .030 0.65 bsc .026 3 bsc .118 5 bsc .200
3959 dmos full-bridge pwm motor driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 12 motor drivers function output ratings* part number ? integrated circuits for brushless dc motors 3-phase power mosfet controller 28 v 3933 3-phase power mosfet controller 40 v 3935 3-phase power mosfet controller 50 v 3932 & 3938 3-phase back-emf controller/driver 900 ma 14 v 8904 3-phase pwm current-controlled dmos driver 3.0 a 50 v 3936 integrated bridge drivers for dc and bipolar stepper motors pwm current-controlled dual full bridge 500 ma 18 v 3965 dual full bridge with protection & diagnostics 500 ma 30 v 3976 pwm current-controlled dual full bridge 650 ma 30 v 3966 pwm current-controlled dual full bridge 650 ma 30 v 3968 microstepping translator/dual full bridge 750 ma 30 v 3967 pwm current-controlled dual full bridge 750 ma 45 v 2916 pwm current-controlled dual full bridge 750 ma 45 v 2919 pwm current-controlled dual full bridge 750 ma 45 v 6219 pwm current-controlled dual full bridge 800 ma 33 v 3964 pwm current-controlled dual dmos full bridge 1.0 a 35 v 3973 pwm current-controlled full bridge 1.3 a 50 v 3953 pwm current-controlled dual full bridge 1.5 a 45 v 2917 pwm current-controlled dmos full bridge 1.5 a 50 v 3948 pwm current-controlled microstepping full bridge 1.5 a 50 v 3955 pwm current-controlled microstepping full bridge 1.5 a 50 v 3957 pwm current-controlled dual dmos full bridge 1.5 a 50 v 3972 pwm current-controlled dual dmos full bridge 1.5 a 50 v 3974 pwm current-controlled full bridge 2.0 a 50 v 3952 pwm current-controlled dmos full bridge 2.0 a 50 v 3958 microstepping translator/dual dmos full bridge 2.5 a 35 v 3977 pwm current-controlled dmos full bridge 3.0 a 50 v 3959 unipolar stepper motor & other drivers unipolar stepper-motor translator/driver 1.0 a 46 v 7050 unipolar stepper-motor translator/driver 1.25 a 50 v 5804 unipolar stepper-motor quad drivers 1.5 a 46 v 7024 & 7029 unipolar microstepper-motor quad driver 1.5 a 46 v 7042 unipolar stepper-motor quad driver 1.8 a 50 v 2540 unipolar stepper-motor translator/driver 2.0 a 46 v 7051 unipolar stepper-motor quad driver 3.0 a 46 v 7026 unipolar microstepper-motor quad driver 3.0 a 46 v 7044 unipolar stepper-motor translator/driver 3.0 a 46 v 7052 * current is maximum specified test condition, voltage is maximum rating. see specification for sustaining voltage limits or over-current protection voltage limits. negative current is defined as coming out of (sourcing) the output. ? complete part number includes additional characters to indicate operating temperature range and package style. also, see 3175, 3177, 3235, and 3275 hall-effect sensors for use with brushless dc motors.

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